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Installation and Operation Manual Chapter 1 Introduction

ASM-40 Ver. 1.0 Functional Description 1-5

INT

TXD

RXD

TXD

EXT

RCV

TXFIFO

TX TX

TXD

RXD

TC & RC

EXT CLK

FIFO

ASM-40

SM-40

ASM-40

Clock Recovery

TC & RC

Clock Recovery

PLL

TC & RC

RCV

TXD

RXD

RX FIFO

SM-40

Clock Recovery

TC & RC

PLL

Figure 1-6. ASM-40 Clock Configuration

G.703-HDB3 Interface Timing

The received data from the analog side is output on the DTE interface with a

jitter-free clock for TC & RC (see

Figure 1-7

and

Figure 1-8

). The transmit data on

the analog side is the input data from the DTE interface. The G.703-HDB3

recovered clock (from the input data) is used as an input clock for the transmit

FIFO, as shown in

Figure 1-7.

The same FIFO used for external clock is always

present when using the G.703-HDB3 interface).

Using the internal or receive clock, provisions must be made to loop back (on the

DTE side) the incoming clock (data and clock out) to the transmit data (data and

clock inputs). Refer to

Figure 1-8

, for clock configuration.

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 115 116

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